1. Field of the Invention
The present invention generally relates to digital memory and, more particularly, to associative or content-addressable memory (CAM) cell structures.
2. Description of the Related Art
A common type of READ/WRITE digital memory device is a random access memory (RAM) integrated circuit. In RAM devices, an address provided by a computer's central processing unit (CPU) or other addressing device specifies a unique storage location within the RAM array. The storage location can be a single bit, or a number of associated bits arranged as a digital word. Addresses are contiguous within a RAM device. As such, the RAM addressing structure is said to be unambiguous in that a RAM address specifies one--and only one--data storage location. Thus, there is a direct correlation between the width of the address field and memory storage capacity.
RAM devices are not suited for use in systems which process associative data. For example, the sequential access to data when addressing RAM is inefficient for systems involved in pattern recognition, natural language recognition, sparse matrix processing, and database interrogation. In such cases, the address associated with desired data may not be known. Hence, it may be desirable to interrogate the memory by supplying the desired data, after which the memory responds by indicating the absence or presence of the data and their associated address.
Another type of memory device which has been developed to have ambiguous and noncontiguous addressing is the CAM. Storage locations within CAM devices are addressed by an incoming bit pattern called a "comparand." Part of each storage location within the CAM can be considered to contain an associated address, whereas the remainder of the storage location can be considered to contain associated data. The comparand is compared, in parallel, to associated addresses of all storage locations: if the associated address has the desired relationship to the comparand, the associated data at that location are addressed.
Alternatively, the comparand can be compared to the entirety of the storage locations to detect whether the particular bit pattern corresponding to the comparand is stored within the CAM device. In other words, a number of storage locations within the CAM may contain the same associated address. "Masking" is used to mask certain bits of the comparand during a comparison function and to mask certain bits of the address during a WRITE operation. For example, during a COMPARE mode function, masked bits can be forced to provide a true comparison, if so desired. Thus, the system designer is permitted to use ambiguous content addressing.
CAM architectures and uses are described in U.S. patent application Ser. Nos. 807,577 (filed Dec. 11, 1985) and 817,230 (filed Jan. 8, 1986), assigned to the common assignee of the present invention.
A problem associated with known CAM devices is that the individual memory cell is much larger than a standard RAM cell. A static RAM cell (SRAM) typically uses a common flip-flop for each cell. A common cell has four transistors, two resistors and five interconnections. A typical dynamic RAM (DRAM) cell needs only a single storage component, such as a capacitor, and an accessing component, such as a transistor, which can be turned ON or OFF during memoy access. While the DRAM cell provides the capability of much denser and, therefore, large memory arrays on the same size chip, the capacitor-stored charges decay in a fraction of a second. Therefore, the charges have to be "refreshed" regularly. The CAM cell must also be able to signal exact matches or mismatches, as well as to be masked.
One CAM cell is taught by MUNDY, in U.S. Pat. No. 3,701,980. This structure uses four transistors. While simple, this structure has a low storage charge and provides little or no signal margin. It is, therefore, subject to soft errors and suffers from less than optimal performance.
Another CAM cell is shown in the IEEE IEDM 85, at pages 284-287: "Dynamic Cross-Coupled Bitline Content Addressable Memory Cell for High Density Arrays," by Wade and Sodini. Wade and Sodini discuss the problems of MUNDY and present an n-type metal-oxide-semiconductor structure (NMOS) having five transistors. This structure is concerned with the use of three states, 1, 0, and DON'T CARE; i.e., a CAM storage location will match the data on the bitlines if they both have the same logical value or if either the cell or bitline is a DON'T CARE. The storage on the gate of the ON transistor provides a higher storage node capacitance than in a standard DRAM cell.
Another CAM cell is taught in U.S. Pat. No. 4,404,653 (ZEHNER). The purpose of the structure of ZEHNER over the prior art is apparently to provide an additional TAG function.
The complexity of the known CAM cell structures has prevented the CAM devices from matching the density of SRAM devices and the speed and low-power requirements of common DRAM circuits, resulting in a high cost-per-bit factor. Therefore, there is a need for improvement in the CAM cell structures.